New CoWoS-L Supplier, BESI CMD Spaces, Intel EMIB-T Flaw, Pegatron US Investment
Chips & Wafers Weekly Update
This week we will leave our CoWoS deep-dive to the end, due to it’s length and portion that is paywalled.
BESI CMD Spaces
Yesterday BESI (BE Semiconductor) held it’s annual Capital Markets Day and put on a great show.
On Wednesday, we hosted an 𝕏 Spaces to talk about BESI and what to look out for during the CMD. We covered the company product portfolio, main applications and future opportunities across the Advanced Packaging landscape.
The CMD presentations provided helpful insights into BESI’s long-term assumptions and what their customers are telling them about future product roadmaps in terms of packaging solutions and requirements.
Next week, we will put out a thorough analysis on our thoughts and opinions surrounding the CMD and how it matches some of the topics we discussed during our Spaces talk. Stay tuned.
But short reminder - there is no AI without AP!
Also, we will try to do some more business breakdowns of enabling companies in the semi supply chain that are lesser known. Have a company you’d like us to discuss? Let us know!
Intel EMIB-T. New Generation, Old Flaw
Earlier this week, there was a new IEEE article around INTC 0.00%↑’s new EMIB-T bridge packaging solution that was discussed during ECTC.
After the reporting, we put out a long thread on 𝕏 exploring the key flaw that EMIB-T shares with EMIB 1.0: the embedded bridges.
We recommend reading the full thread to get a clearer picture of the technology and how it stacks up (pun intended) against TSM 0.00%↑’s CoWoS-L. In short, EMIB embeds its interconnect bridge within the package substrate—a choice that increases fabrication complexity and drives up the ASP per substrate. In contrast, CoWoS-L places the LSI interconnects above the substrate, allowing for greater standardization and significantly lower substrate cost and complexity.
Be sure to read the full thread.
Pegatron US Investments
With AI server demand booming across North America, Pegatron is weighing the setup of a new manufacturing facility in the US.
The company says the move would help meet growing AI infrastructure needs while also softening the blow of US tariffs. This follows its recent manufacturing expansion into Mexico, where mass production of servers is expected to begin by Q3 2025.
This is yet another example of a semiconductor supply chain player shifting capacity to the US in response to tariffs. Moves like this are likely to be well-received by the current administration in the short term, but the real question is whether these companies truly intend to commit long-term capacity to the US If so, what does that mean for all the capacity already built in Taiwan and other non-China geographies?
Food for thought.
New CoWoS-L Supplier & Opportunity Size
Earlier this week, we shared on X that we were preparing a piece on a new CoWoS supplier—here it is.
Wait Up - What is CoWoS?
CoWoS (Chip-on-Wafer-on-Substrate) is TSMC’s advanced 2.5D packaging technology that allows multiple chips—such as GPUs, CPUs, and high-bandwidth memory (HBM)—to be mounted side by side on a silicon interposer, which is then attached to a substrate. This enables ultra-high-bandwidth connections between chips that would be impossible with traditional packaging.
CoWoS is necessary because modern AI and HPC workloads demand immense memory bandwidth and compute density. As Moore’s Law slows, simply shrinking transistors isn’t enough—so chipmakers are turning to advanced packaging like CoWoS to integrate more compute and memory into a tight footprint, reduce latency, and improve performance per watt.
CoWoS-S
CoWoS-S is the original and most widely adopted variant of TSMC’s CoWoS family. It uses a silicon interposer as the interconnect method between compute and memory, which is then mounted onto a standard organic substrate using conventional flip-chip bonding techniques.
In this setup, logic dies are placed alongside one or more HBM stacks on a large silicon interposer that handles high-speed signal routing between them. This interposer is then bonded to the package substrate, which connects to the PCB. CoWoS-S supports relatively large interposer sizes, enabling multi-die integration and wide memory interfaces critical for AI and HPC workloads.
CoWoS-S was TSMC’s foray into 2.5D packaging and became the enabling technology behind the AI hardware revolution as it was the packaging technique used for Nvidia’s Hopper series.
CoWoS-S has served TSMC well, but increasing die and package sizes (Blackwell is larger than Hopper, and GB200 uses not one but two GPUs) have made interposer stitching at those sizes costly and, in some cases, physically unfeasible, pushing TSMC to innovate toward a new CoWoS architecture.
Enter CoWoS-L
CoWoS-L is TSMC’s next-generation packaging innovation, created in response to the limitations of the S platform. As Nvidia and others push toward ever-larger multi-die designs, the traditional approach of using a single large silicon interposer becomes untenable. These interposers are extremely expensive, difficult to manufacture at high yield, and mechanically fragile as their size grows.
To address this, CoWoS-L replaces the monolithic interposer with smaller, modular silicon bridges - also known as LSI (Local Silicon Interconnect), that locally connect the dies. This allows for much more flexibility in package design, improves manufacturing yield, and helps reduce cost. It also enables the integration of more components in a single package, such as the dual logic dies and six HBM stacks in Nvidia’s GB200—something far more challenging with CoWoS-S.
CoWoS Process Differences & Vendors
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